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SUMMARY:Development of the Read-out ASIC for Muon Chambers
DTSTART;VALUE=DATE-TIME:20151010T070000Z
DTEND;VALUE=DATE-TIME:20151010T071500Z
DTSTAMP;VALUE=DATE-TIME:20260308T182021Z
UID:indico-contribution-290@cern.ch
DESCRIPTION:Speakers: Malankin Evgeny (NRNU MEPHI)\nA front-end prototype 
 ASIC for muon chambers is presented. ASIC was designed and prototyped in C
 MOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog p
 rocessing channels\, each consisting of preamplifier\, two shapers (fast a
 nd slow)\,differential comparator and an area efficient 6 bit SAR ADC with
  1.2 mW power consunption at 50 Msps. The chip also includes the threshold
  DAC and digital serializer. The design has the following features: dynami
 c range of 100 fC\, channel hit rate of 2 MHz\, ENC of 1000 e- at 50 pF\, 
 power comsumption of 10 mW per channel\, 6 bit SAR ADC.\n\nhttps://indico.
 particle.mephi.ru/event/2/contributions/290/
LOCATION:Milan Hotel 4* Verdi
URL:https://indico.particle.mephi.ru/event/2/contributions/290/
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