BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CERN//INDICO//EN
BEGIN:VEVENT
SUMMARY:Development of ASICs for experiments at NICA
DTSTART;VALUE=DATE-TIME:20221201T163000Z
DTEND;VALUE=DATE-TIME:20221201T165000Z
DTSTAMP;VALUE=DATE-TIME:20260720T010648Z
UID:indico-contribution-3138@cern.ch
DESCRIPTION:Speakers: Eduard Atkin (MEPhI)\, Artur Serazetdinov (MEPhI)\nT
 he results of development and laboratory testing of a prototype data conce
 ntrator integrated circuit (ASIC HUBv1) are presented. HUBv1 was developed
  for processing of signals from the detector chips of the time-projection 
 chamber of the MPD experiment (NICA\, Dubna). The main target of this ASIC
  is uninterrupted processing and serialization of digital output data from
  two SAMPA detector chips and their transmission via AWG-36 type cables up
  to 1 m long at the speed of 2.56 Gbit/s to the data acquisition controlle
 r board. Eight data and six SLVS clock ports are used to connect the SAMPA
  chips. The received data is error-checked using Hamming code and is avail
 able on the two high-speed CML output ports\, each with bandwidth up to 2.
 56 Gbps. Both SAMPA and SIMC chips are controlled by issuing control comma
 nds via the high-speed CML or slow SPI interfaces.\nThe HUBv1 prototype wa
 s manufactured using TSMC's 65 nm CMOS technology and packaged in CPGA120-
 type packages. The total power consumption of the ASIC does not exceed 500
  mW. The results of laboratory testing of the chip and radiation resistanc
 e testing of the analog blocks are presented.\n\nThe development of key bu
 ilding blocks of a prototype application specific integrated circuit (ASIC
 ) for the SPD experiment at NICA Nuclotron (Dubna) is presented. It was de
 signed as an 8-channel fully differential amplifier-discriminator which co
 uld be used as a front-end electronics for resistive plate chambers as wel
 l as for time-of-flight measurements.\n\nThe ASIC has an architecture simi
 lar to the NINO chip developed at CERN. Each channel consists of  the foll
 owing functional blocks: a current preamplifier-shaper with the peaking ti
 me of 500 ps\, low-frequency feedback with built-in threshold preset circu
 it\, few additional amplification stages\, pulse stretcher\, LVDS output s
 tage and some other supporting blocks. The chip is optimized for the input
  capacitance in range 1-10 pF\, has adjustable threshold of 10-450 fC\, an
 d adjustable stretching time of 1-100 ns. The equivalent noise charge is n
 ot more than 2500 e at input capacitance up to 10 pF. The design was optim
 ized for reducing front-edge jitter (less than 15 ps). Both schematic and 
 layout of designed blocks are presented\, simulation results are shown. PV
 T variation and Monte-Carlo mismatch plots are also given.\n\nThe developm
 ent was conducted in the 180 nm CMOS  process PDK of Mikron fab at Zelenog
 rad.  GDSII file was submitted to the factory at late August 2022.\n\nhttp
 s://indico.particle.mephi.ru/event/275/contributions/3138/
LOCATION:Hotel Intourist Kolomenskoye 4* Moskvorechye 1
URL:https://indico.particle.mephi.ru/event/275/contributions/3138/
END:VEVENT
END:VCALENDAR