Speaker
Dr.
Maxim Gorbunov
(SRISA, NRNU MEPhI)
Description
It is well-known that there is a trade-off between performance and power consumption in onboard computers. The fault-tolerance is another important factor affecting performance, chip area and power consumption. Involving special SRAM cells and error-correcting codes is often too expensive with relation to the performance needed. We discuss the possibility of finding the optimal solutions for modern onboard computer for scientific apparatus focusing on multi-level cache memory design.
Primary author
Dr.
Maxim Gorbunov
(SRISA, NRNU MEPhI)
Co-authors
Mr.
Andrey Antonov
(SRISA)
