Speaker
Mr.
Malankin Evgeny
(NRNU MEPHI)
Description
A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of preamplifier, two shapers (fast and slow),differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consunption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power comsumption of 10 mW per channel, 6 bit SAR ADC.
| Presentation type | Section talk (10+5 min) |
|---|
Primary author
Mr.
Malankin Evgeny
(NRNU MEPHI)
Co-authors
Mr.
Alexander Gusev
(NRNU MEPhI)
Dr.
Alexander Voronin
(SINP MSU)
Mr.
Dmitry Normanov
(NRNU Mephi)
Dr.
Eduard Atkin
(National Research Nuclear University MEPhI)
Mr.
Ilias Sagdiev
(NRNU MEPhI)
Mr.
Ivan Bulbakov
(NRNU MEPhI)
Mr.
Oleg Shumkin
(NRNU MEPhI)
Mr.
Pavel Ivanov
(NRNU MEPhI)
Mr.
Sergey Vinogradov
(NRNU MEPhI)
Mr.
Vitaly Shumikhin
(NRNU MEPhI)
